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RT8801 preliminary 1 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively multi-phase pwm controller for cpu core power supply with serial programming interface general description the RT8801 is a multi-phase synchronous buck controller which is implemented with full control functions for intel ? vr10.0/10.1-compliant cpu. the RT8801 could be operated with 2, 3 or 4 buck switching stages operating in interleaved phase set automatically. the multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. RT8801 is one of richtek cpu core power solutions which integrates a specific series programming interface for the controller operation configuration. there are several registers implemented for the specific parameters configuration including vid for core power, and signal for load current indication. user can program the configuration of the parameters easily via the specific programming interface. with the implementation of RT8801, the part provides more flexibility and feature for customers advanced segment product design. the RT8801 applies the dcr sensing technology newly as well; with such a topology, the RT8801 extracts the dcr of output inductor as sense component to deliver a more precise load line regulation and better thermal balance for next generation processor application. for current sense setting, droop tuning, v core initial offset and over current protection are independent to compensation circuit of voltage loop. the feature greatly facilitates the flexibility of cpu power supply design and tuning. the dac output of RT8801 supports vrd10.x with 6-bit vid input, precise initial value & smooth v core transient at vid jump. the ic monitors the v core voltage for over-voltage protection. soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system. the RT8801 comes to the package of vqfn-32l 5x5. features z z z z z multi-phase power conversion with automatic phase selection z z z z z 6-bits vrd10.x dac output with active droop compensation for fast load transient z z z z z smooth v core transition at vid jump z z z z z power stage thermal balance by dcr current sense z z z z z hiccup mode over-current protection z z z z z adjustable switching frequency (50khz to 400khz per phase) z z z z z under-voltage lockout and soft-start z z z z z high ripple frequency times channel number z z z z z 2-wires programming interface z z z z z software programmable vid z z z z z 32-lead vqfn package z z z z z rohs compliant and 100% lead (pb)-free applications z intel ? vr10.x-compliant processors voltage regulator z low output voltage, high power density dc-dc converters z voltage regulator modules ordering information note : richtek pb-free and green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ` 100% matte tin (sn) plating. package type qv : vqfn-32l 5x5 (v-type) operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard) RT8801
RT8801 preliminary 2 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively registers 0x00 hi-i setting registers; default 0x00 bit4-0 : pin configurations (top view) vqfn-32l 5x5 bit4 bit3 bit2 bit1 bit0 vid offset (mv) 0 0 0 0 0 0 0 0 0 0 1 12.5 0 0 0 1 0 25 0 0 0 1 1 37.5 0 0 1 0 0 50 0 0 1 0 1 62.5 0 0 1 1 0 75 0 0 1 1 1 87.5 0 1 0 0 0 100 0 1 0 0 1 112.5 0 1 0 1 0 125 0 1 0 1 1 137.5 0 1 1 0 0 150 0 1 1 0 1 162.5 0 1 1 1 0 175 0 1 1 1 1 187.5 bit4 bit3 bit2 bit1 bit0 vid offset (mv) 1 0 0 0 0 200 1 0 0 0 1 212.5 1 0 0 1 0 225 1 0 0 1 1 237.5 1 0 1 0 0 250 1 0 1 0 1 262.5 1 0 1 1 0 275 1 0 1 1 1 287.5 1 1 0 0 0 300 1 1 0 0 1 312.5 1 1 0 1 0 325 1 1 0 1 1 337.5 1 1 1 0 0 350 1 1 1 0 1 362.5 1 1 1 1 0 375 1 1 1 1 1 400 slot_occ pwm3 ad_sel gnd ic_out fb clk data csp2 adj csp4 csp3 csp1 pwm1 pwm2 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9101112 14 13 28 27 26 25 24 22 23 32 31 30 29 gnd pwm4 vid1 vid125 vid0 vid2 vid3 vid4 vdd csn voss comp sgnd dvd ss pgood rt 33 rst
RT8801 preliminary 3 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively 0x01 core current. default 0x00 (read only). the core current full scale is over current trigger point. bit6-0 : show core voltage current. 0x03 misc. default 0x04. bit2 : slot_occ detection. this bit be written clear and only can be written 0. 0 : normal 1 : slot_occ ever be pulled high bit1 : the reset pin ever be pull low when bit0 = 1 and only can be written 0. 0 : never issue reset 1 : ever issue reset bit0 : reset control. when this bit be write 1, the watching dog timer (reset pin) will repeat counter 1400ms then pull low 200ms.reset pin be pull low, if this bit = 1 will reset all registers to default exception misc(index 0x03). 0 : disable 1 : enable note : if slot_occ pin = 1 reset all registers value to default. product information registers (read only) 0x13 revision_id 0x00 rst enable 0x03 bit 0 7 x t delay t delay wd timer rst
RT8801 preliminary 4 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively typical application circuit gnd slot_occ ad_sel gnd ic_out fb rst clk data pwm3 csp2 adj csp4 csp3 csp1 pwm1 pwm2 csn voss comp sgnd dvd ss pgood rt pwm4 vid1 vid125 vid0 vid2 vid3 vid4 vdd v core 680uf x 10 10uf x 18 1 3 2 8 7 21 20 19 18 17 16 15 9101112 14 13 28 27 26 25 24 22 23 32 31 30 29 slot_occ 5vsb vid4 vid3 vid2 vid1 vid0 vid12.5 0.1uf clk data 10nf 15k 33pf 10nf 3k 100k 0.1uf 12k 27k 27k 3k v cc 12v 330 nc nc nc nc nc 0 0 v core in4148 5 5vsb 4.7k nc 6 4 v cc 3v 4.7k v cc 5v 4.7k boot1 ugate1 phase1 lgate1 vcc rt9607pqv 11 14 2 13 12 ugate2 phase2 lgate2 boot2 pwm2 9 5 10 6 7 pwm1 pvcc gnd 16 1 15 pgnd 4 1uf 12v 1uf 10 ipd09n03 0.6uh pvcc12v 0 ipd06n03 2.2 0.01uf 1uf 1500uf 0 ipd09n03 0.6uh 0 ipd06n03 2.2 0.01uf 1uf 1500uf 0 1uf nc 3 8 boot1 ugate1 phase1 lgate1 vcc rt9607pqv 11 14 2 13 12 ugate2 phase2 lgate2 boot2 pwm2 9 5 10 6 7 pwm1 pvcc gnd 16 1 15 pgnd 4 1uf 12v 1uf 10 ipd09n03 0.6uh pvcc12v 0 ipd06n03 2.2 0.01uf 1uf 1500uf 0 ipd09n03 0.6uh 0 ipd06n03 2.2 0.01uf 1uf 1500uf 0 1uf nc 3 8 RT8801 200 nc ntc
RT8801 preliminary 5 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively functional pin description slot_occ (pin 1) cpu socket occupied; the signal is defined to indicate if the cpu has been changed/ removed and it will reset all chip. there is one register implemented for the status indication. the register will be reset when the v dd power removed or cpu changed/removed. the pin is implemented as an input, ttl level, and active-low signal. data (pin 2), clk (pin 3) 2-wires programming interface. rst (pin 4) this pin be pull low (the watching dog = low), it will reset some register, when 0x03 bit 0 be setting. ad_sel (pin 5) the pin select series bus address. pin =1,address = 0x5e & pin = 0, address = 0x5c. gnd (pin 6, bottom pad) chip power ground. ic_out (pin 7) the pin is defined as a reference current output. a capacitor is attached to set the de fault watching dog low pluse time. write the index 0x03 bit0 = 1 delay 7 times t delay time then issue t delay low pluse. fb (pin 8) the pin is defined as an inverting input of internal error amplifier. comp (pin 9) the pin is defined as an output of the error amplifier and an input of the pwm comparator. sgnd (pin 10) difference ground sense of v core . voss (pin 11) v core initial value offset. connect this pin to gnd with a resistor to set the offset value. c_out c_out out delay x v i c t where = dvd (pin 12) hardware adjustable system power uvlo detection; input pin; the internal trip threshold = 0.9v at v dvd rising. ss (pin 13) the pin is defined to set soft-start ramp rate; a capacitor is attached to set the start time interval. pull this pin lower than 1.0v (ramp valley of saw-tooth wave in pulse width modulator) will shut the converter down. pgood (pin 14) power good indication. pgood is an open drain output. pgood will go high impedance when ss voltage greater than 3.7v and no fault occurs. rt (pin 15) default operation switching frequency setting. a resistor is attached to set the default operation frequency. csn (pin 16) the pin is defined to sense load current of cpu. the pin should be connected to the output node of choke. adj (pin 17) pin for active droop adjustment. an external resistor is attached to gnd for load droop setting. csp1 (pin 21), csp2 (pin 20), csp3 (pin 19), csp4 (pin 18) current sense inputs from the individual converter channels. pwm1 (pin 22), pwm2 (pin 23), pwm3 (pin 24), pwm4 (pin 25) pwm outputs for each phase switching drive. vdd (pin 26) chip powers supply. connect this pin to a 5vsb or vcc5 supply.
RT8801 preliminary 6 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively function block diagram oscillator & ramp generator + + + + + + sum/m pwm1 pwm2 pwm3 droop tune current correction dac vid1 vid3 vid4 vid125 vid0 vid2 slot_occ sgnd ad_sel pgood dvd rt rst gnd vdd soft start & pgood - + + - csn csp1 csp2 csp3 pwm logic pwmcp + - pwm logic pwmcp + - pwm logic pwmcp + - pwm logic pwmcp + - pwm4 m u x csp4 mux + + digital logic power on reset ss fb ea gm clk comp ic_out voss data ovp trip point offset current source/sink adj wd timer ocp detection ocp ocp inh vid4 (pin 27), vid3 (pin 28), vid2 (pin 29), vid1 (pin 30), vid0 (pin 31), vid125 (pin 32) dac voltage identification; input; the vid0~4 is implemented for vrm9.0 (5-bits) dac identification; the vid0~4, vid125 is implemented for vrm10.x (6-bits) dac identification. the pins are internally pulled to 1.2v (pull high 50 a) if left open. gnd [exposed pad (33)] the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
RT8801 preliminary 7 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively table 1. output voltage program to be continued pin name vid4 vid3 vid2 vid1 vid0 vid125 nominal output voltage dacout 1 1 1 1 1 x no cpu 0 1 0 1 0 0 0.8375v 0 1 0 0 1 1 0.850v 0 1 0 0 1 0 0.8625v 0 1 0 0 0 1 0.875v 0 1 0 0 0 0 0.8875v 0 0 1 1 1 1 0.900v 0 0 1 1 1 0 0.9125v 0 0 1 1 0 1 0.925v 0 0 1 1 0 0 0.9375v 0 0 1 0 1 1 0.950v 0 0 1 0 1 0 0.9625v 0 0 1 0 0 1 0.975v 0 0 1 0 0 0 0.9875v 0 0 0 1 1 1 1.000v 0 0 0 1 1 0 1.0125v 0 0 0 1 0 1 1.025v 0 0 0 1 0 0 1.0375v 0 0 0 0 1 1 1.050v 0 0 0 0 1 0 1.0625v 0 0 0 0 0 1 1.075v 0 0 0 0 0 0 1.0875v 1 1 1 1 0 1 1.100v 1 1 1 1 0 0 1.1125v 1 1 1 0 1 1 1.125v 1 1 1 0 1 0 1.1375v 1 1 1 0 0 1 1.150v 1 1 1 0 0 0 1.1625v 1 1 0 1 1 1 1.175v 1 1 0 1 1 0 1.1875v 1 1 0 1 0 1 1.200v 1 1 0 1 0 0 1.2125v
RT8801 preliminary 8 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively pin name vid4 vid3 vid2 vid1 vid0 vid125 nominal output voltage dacout 1 1 0 0 1 1 1.225v 1 1 0 0 1 0 1.2375v 1 1 0 0 0 1 1.250v 1 1 0 0 0 0 1.2625v 1 0 1 1 1 1 1.275v 1 0 1 1 1 0 1.2875v 1 0 1 1 0 1 1.300v 1 0 1 1 0 0 1.3125v 1 0 1 0 1 1 1.325v 1 0 1 0 1 0 1.3375v 1 0 1 0 0 1 1.350v 1 0 1 0 0 0 1.3625v 1 0 0 1 1 1 1.375v 1 0 0 1 1 0 1.3875v 1 0 0 1 0 1 1.400v 1 0 0 1 0 0 1.4125v 1 0 0 0 1 1 1.425v 1 0 0 0 1 0 1.4375v 1 0 0 0 0 1 1.450v 1 0 0 0 0 0 1.4625v 0 1 1 1 1 1 1.475v 0 1 1 1 1 0 1.4875v 0 1 1 1 0 1 1.500v 0 1 1 1 0 0 1.5125v 0 1 1 0 1 1 1.525v 0 1 1 0 1 0 1.5375v 0 1 1 0 0 1 1.550v 0 1 1 0 0 0 1.5625v 0 1 0 1 1 1 1.575v 0 1 0 1 1 0 1.5875v 0 1 0 1 0 1 1.600v table 1. output voltage program note: (1) 0 : connected to gnd (2) 1 : open (3) x : don ' t care
RT8801 preliminary 9 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively absolute maximum ratings (note 1) z supply voltage, v dd ----------------------------------------------------------------------------------------- 7v z input, output or i/o v oltage -------------------------------------------------------------------------------- gnd - 0.3v to v dd + 0.3v z power dissipation, p d @ t a = 25 c vqfn-32l 5x5 ------------------------------------------------------------------------------------------------ 2.78w z package thermal resistance (note 4) vqfn-32l 5x5, ja ------------------------------------------------------------------------------------------- 36 c/w z junction temperature ---------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c z storage temperature range ------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 2) hbm (human body mode) --------------------------------------------------------------------------------- 2kv mm (ma chine mode) ----------------------------------------------------------------------------------------- 200v electrical characteristics recommended operating conditions (note 3) z supply voltage, v dd ----------------------------------------------------------------------------------------- 5v 10% z ambient temperature range ------------------------------------------------------------------------------- 0 c to 70 c z junction temperature range ------------------------------------------------------------------------------- 0 c to 125 c to be continued parameter symbol test conditions min typ max units v dd supply current nominal supply current i dd pwm 1,2,3,4 open -- 12 16 ma power-on reset por threshold v ddrth v dd rising 4.0 4.2 4.5 v hysteresis v ddhys 0.2 0.5 -- v trip (low to high) v dvdtp enable 0.8 0.9 1.0 v v dvd threshold hysteresis v dvdhys -- 70 -- mv oscillator free running frequency f osc r rt = 22.5k 250 300 350 khz frequency adjustable range f osc_adj 50 -- 400 khz ramp amplitude v osc r rt = 22.5k -- 1.9 -- v ramp valley v rv 0.7 1.0 -- v maximum on-time of each channel 62 66 75 % rt pin voltage v rt r rt = 22.5k 1.7 1.8 1.9 v reference and dac v dac 1v ? 1 -- +1 % dacout voltage accuracy v dac v dac < 1v ? 10 -- +10 mv dac (vid0-vid125) input low v ildac -- -- 0.3 v dac (vid0-vid125) input high v ihdac 0.8 -- -- v (v dd = 5v, t a = 25c, unless otherwise specified)
RT8801 preliminary 10 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively parameter symbol test conditions min typ max units offset voltage ? 3 -- 3 % voss pin voltage v voss r voss = 100k 1.6 1.7 1.8 v error amplifier dc gain -- 85 -- db gain-bandwidth product gbw -- 10 -- mhz slew rate sr comp = 10pf -- 3 -- v/ s current sense gm amplifier csn full scale source current i ispfss 150 -- -- a csn current for ocp -- 150 -- a protection ss current i ss v ss = 1v 8 13 18 a over-voltage trip sen dacout offset v v + v ovt 130 140 150 % delay time wd timer, t dl (c l = 100nf) -- 200 -- ms wd timer, t dh (c l = 100nf) -- 1400 -- ms power good output low voltage v pgoodl i pgood = 4ma -- -- 0.2 v note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard.
RT8801 preliminary 11 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively typical operating characteristics adjustable frequency 0 50 100 150 200 250 300 350 400 450 0 20 40 60 80 100 120 r rt (k ) f osc (khz) (k ) linearity of each pwm 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 0 500 1000 1500 2000 2500 3000 3500 pulse width (ns) v comp (v) pwm2 pwm3 pwm1 pwm4 f osc = 200k load transient response time (5 s/div) v core phase i out v adj ch1: (500mv/div) ch2: (10v/div) ch3: (50a/div) ch4: (100mv/div) load transient response time (5 s/div) v core phase1 phase2 phase3 ch1: (500mv/div), ch2: (10v/div) ch3: (10v/div), ch4: (10v/div) ch3:(10v/div) ch4:(1v/div) power-off @ i out = 60a time (10 s/div) v comp pwm ugate lgate ch1:(5v/div) ch2:(20v/div) power-on @ i out = 60a time (10ms/div) ugate lgate v ss pwm ch3:(20v/div) ch4:(10v/div) ch1:(5v/div) ch2:(5v/div)
RT8801 preliminary 12 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively ch1:(5v/div) ch2:(5v/div) relationship between inductor current and v adj time (25ms/div) v ss pwm v adj i l ch3:(50mv/div) ch4:(20a/div)
RT8801 preliminary 13 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively application information RT8801 is a multi-phase dc/dc controller that precisely regulates cpu core voltage and balances the current of different power channels. the converter consisting of RT8801 and its companion mosfet driver rt9607/ rt9607a provides high quality cpu power and all protection functions to meet the requirement of modern vrm. voltage control RT8801 senses the cpu v core by sgnd pin to sense the return of cpu to minimize the voltage drop on pcb trace at heavy load. ovp is sensed at fb pin. the internal high accuracy vid dac provides the reference voltage for vrd10.x compliance. control loop consists of error amplifier, multi-phase pulse width modulator, driver and power components. as conventional voltage mode pwm controller, the output voltage is locked at the v ref of error amplifier and the error signal is used as the control signal of pulse width modulator. the pwm signals of different channels are generated by comparison of ea output and split-phase sawtooth wave. power stage transforms v in to output by pwm signal on-time ratio. current balance RT8801 senses the inductor current via inductor's dcr for channel current balance and droop tuning. the differential sensing gm amplifier converts the voltage on the sense component (can be a sense resistor or the dcr of the inductor) to current signal into internal balance circuit. the current balance circuit sums and averages the current signals and then produces the balancing signals injected to pulse width modulator. if the current of some power channel is larger than average, the balancing signal reduces that channels pulse width to keep current balance. the use of single gm amplifier via time sharing technique to sense all inductor currents can reduce the offset errors and linearity variation between gms. thus it can greatly improve signal processing especially when dealing with such small signal as voltage drop across dcr. load droop the sensed power channel current signals regulate the reference of dac to form an output voltage droop proportional to the load current. the droop or so call ? active voltage positioning ? can reduce the output voltage ripple at load transient and the lc filter size. fault detection the chip detects fb for over voltage. the ? hiccup mode ? operation of over current protection is adopted to reduce the short circuit current. the inrush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. phase setting and converter start u p RT8801 interfaces with companion mosfet drivers (like rt9619, rt9607 series) for correct converter initialization. the tri-state pwm output (high, low and high impedance) senses its interface voltage when ic por acts (both vdd and dvd trip). the channel is enabled if the pin voltage is 1.2v less than vdd. tie the pwm to vdd and the corresponding current sense pins to gnd or left float if the channel is unused. for example, for 3-channel application, connect pwm4 high. current sensing setting RT8801 senses the current flowing through inductor via its dcr for channel current balance and droop tuning. the differential sensing gm amplifier converts the voltage on the sense component (can be a sense resistor or the dcr of the inductor) to current signal into internal circuit (see figure 1). figure 1. current sense circuit figure 2 is the test circuit for gm. we apply test signal at gm inputs and observe its signal process output at adj pin. figure 3 shows the variation of signal processing of all channels. we observe zero offsets and good linearity between phases. csn c x l c r v i i dcr v c r dcr l = = = l dcr r r csn gmx i x c + - + - v c
RT8801 preliminary 14 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively figure 3. the linearity of gmx figure 4 shows the time sharing technique of gm amplifier. we apply test signal at phase 4 and observe the waveforms at both pins of gm amplifier. the waveforms show time sharing mechanism and the perfomance of gm to hold both input pins equal when the shared time is on. over current protection RT8801 uses an external resistor r csn to set a programmable over current trip point. ocp comparator compares each inductor current with this reference current. RT8801 uses hiccup mode to eliminate fault detection of ocp or reduce output current when output is shorted to ground. figure 5. over current comparator + - i x 150ua ocp comparator figure 2. the test circuit of gm l dcr esr r csn 1k gmx i x v x + - v csp v csn figure 4 time sharing of gm time (1 s/div) pwm3 v csp4 and v csn ch1:(2v/div) ch2:(50mv/div) ch3:(50mv/div) v csp4 v csn gm 0 50 100 150 200 250 300 0 20406080100120140 v x (mv) v adj (mv) figure 6. over current protection at steady state current ratio setting figure 7. application circuit for current ratio setting for some case with preferable current ratio instead of current balance, the corresponding technique is provided. due to different physical environment of each channel, it is necessary t o slightly adjust current loading between channels. figure 7 show s the application circuit of gm for current ratio requirement. applying kvl along l+dcr branch and r1+c//r2 branch: ch1:(5v/div) ch2:(2v/div) ch3:(1v/div) over current protection time (25ms/div) pwm v ss v core
RT8801 preliminary 15 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively l 2 1 c c 2 2 1 c 1 c c 2 c 1 l l i dcr r r r2 v for v r r r dt dv c r v ) dt dv c r v ( r i dcr dt di l + = + + = + + = + look for its corresponding conditions : c (r1//r2) dcr l let i dcr dt di dcr c (r1//r2) i dcr dt di l l l l l = + = + with internal current balance function, this phase would share (r 1 +r 2 )/r 2 times current than other phases. fig ure 8 & 9 show differ ent settings for the power stages. figure 10 shows the performance of current ratio compared with conventional current balance function in figure 11. figure 8. gm4 setting for current ratio function figure 9. gm1~3 setting for current ratio function figure 10 thus if c (r1//r2) dcr l = then l c i dcr r2 r1 r2 v + = figure 11 figure 12. application circuit o f gm current ratio function 0 5 10 15 20 25 30 35 0 153045607590 i out (a) i l (a) i l3 i l4 i l2 i l1 current balance function -5 0 5 10 15 20 25 0 20406080100 i out (a) i l (a) i l1 i l3 i l2 i l4 l dcr esr r csn1 gmx ix + - c r csn2 v csp v csn
RT8801 preliminary 16 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively for load line design, with application circuit in figure 12, it can eliminate the dead zone of load line at light loads. v csp = v out +i l x dcr if gm holds input voltages equal, then v csp = v csn for the lack of sinking capability of gm, r csn2 should be small enough to compensate the negative inductor valley current especially at light loads. vid on the fly with external pull up resistors tied to vid pins, RT8801 converters different vid codes from cpu into output voltage. figure 14 and figure 15 show the waveforms of vid on the fly function. r csn2 85.8k choose r csn2 = 82k assume the negative inductor valley current is ? 5a at no load, then for figure 14 ch1:(5v/div) ch2:(500mv/div) ch3:(500mv/div) ch4:(1v/div) vid on the fly (falling) time (25 s/div) v core pwm v fb vid125 v dac = 1.500, i out = 5a r csn1 = 330 , r ad j = 160 , v out = 1.300v figure 13 csn1 l csn2 l csn2 out csn1 l csn2 l out csn1 l csn2 csn x r dcr i r dcr i r v r dcr i r dcr i v r dcr i r v i + + = + + = + = csn1 l csn2 csn r dcr i r v 330 1m 5a - r 1.3v csn2 load line without dead zone at light loads 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.3 1.31 0 5 10 15 20 25 i out (a) v core (v) r csn2 open r csn2 = 82k figure 16 + - ea 1/4 i voss rb1 v dac -v adj figure 15 ch1:(5v/div) ch2:(500mv/div) ch3:(500mv/div) ch4:(1v/div) vid on the fly (rising) time (25 s/div) v core pwm v fb vid125 v dac = 1.500, i out = 5a
RT8801 preliminary 17 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively error amplifier characteristic for fast response of converter to meet stringent output current transient response, RT8801 provides large slew rate capability and high gain-bandwidth performance. figure 17. ea rising transient with 10pf loading; slew rate = 10v/us ch1:(1v/div) ch4:(2v/div) ea falling slew rate time (250ns/div) v comp v fb output voltage offset function to meet intel ? requirement of initial offset of load line, RT8801 provides programmable initial offset function. external resistor r voss and voltage source at voss pin generate offset current . one quarter of i voss flows through rb1 as shown in figure 16. error amplifier would hold the inverting pin equal to v dac ? v adj . thus output voltage is subtracted from v dac ? v adj for a constant offset voltage. a positive output voltage offset is possible by connecting r voss to vdd instead of to gnd. please note that when r voss is connected to vdd, v voss is v dd ? 2v typically and half of i voss flows through r fb1 . v core is rewritten as: voss voss voss r v i = voss fb1 adj dac core r 4 r - v - v v = voss fb1 adj dac core r r v - v v + = figure 19. gain-bandwidth measurement by signal a divided by signal b + - ea 4.7k b a v ref 4.7k figure 18. ea falling transient with 10pf loading; slew rate = 8v/us ch1:(1v/div) ch2:(2v/div) ea rising slew rate time (250ns/div) v comp v fb pgood function to indicate the condition of multiphase converter, RT8801 provides pgood signal through an open drain connection. as shown in figure 20. pgood pin is externally pulled high when ss pin voltage higher than 3.7v and no fault occurs. figure 20 vdd v pgood r pgood ss > 3.7v
RT8801 preliminary 18 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively where v ramp : ramp amplitude of saw-tooth wave lc filter pole = 1.45khz and esr zero = 3.98khz b. ea compensation network : select r1 = 4.7k, r2 = 15k, c1 = 12nf, c2 = 68pf and use the type 2 compensation scheme shown in figure 21. by calculation, the fz = 0.88khz, fp = 322khz and middle band gain is 3.19 (i.e 10.07db). figure 21. type 2 com pensation network of ea ea rb2 rb1 + - 15k c1 12nf c2 68pf 4.7k design procedure suggestion a.output filter pole and zero (inductor, output capacitor value & esr). b.error amplifier compensation & sawtooth wave amp- litude (compensation network). c.kelvin sense for v core . current loop setting gm amplifier s/h current (current sense component dcr, csn pin external resistor value). vrm load line setting a.droop amplitude (adj pin resistor). b.no load offset (r csn2 ) c.dac offset voltage setting (voss pin & compensation network resistor rb1). power sequence & ss dvd pin external resistor and ss pin capacitor. pcb layout a.kelvin sense for current sense gm amplifier input. b.refer to layout guide for other items. voltage loop setting design example given: apply for four phase converter v in = 12v v core = 1.5v i load (max) = 100a v droop = 100mv at full load (1m load line) ocp trip point set at 40a for each channel (s/h) dcr = 1m of inductor at 25 c l = 1.5 h c out = 8000 f with 5m equivalent esr. 1. compensation setting a. modulator gain, pole and zero : from the following formula: modulator gain = v in /v ramp = 12/1.9 = 6.3 (i.e 16db) the bode plot of ea compensation is shown as figure 23. the bode plot of power stage is shown as figure 24. the total loop gain is in figure 25. 2. over-current protection setting consider the temperature coefficient of copper 3900ppm/ c, 3. soft-start capacitor selection for most application cases, 0.1 f is a good engineering value. = = = 370 r a 150 1.39m 40a r a 150 r dcr i csn csn csn l
RT8801 preliminary 19 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively figure 22. ea frequency response with closed loop gain set at 0db to observe gain-bandwidth product; -3db at 10.86mhz 0db 180 figure 23. the fr equency response of the compensator network 0db -180
RT8801 preliminary 20 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively figure 24. the frequency response of power stage 0db -180 figure 25. the loop gain of converter 0db -180
RT8801 preliminary 21 ds8801-04 august 2007 www.richtek.com all brandname or trademark belong to their owner respectively layout guide place the high-power switching components first, and separate them from sensitive nodes. 1. most critical path: the current sense circuit is the most sensitive part of the converter. the current sense resistors tied to csp1,2,3,4 and csn should be located not more than 0.5 inch from the ic and away from the noise switching nodes. the pcb trace of sense nodes should be parallel and as short as possible. kelvin connection of the sense component (additional sense resistor or inductor dcr) ensures the accurate stable current sensing. kee p well kelvin sen se to en sure the sta ble operation! 2. switching ripple current path: a. input capacitor to high side mosfet. b. low side mosfet to output capacitor. c. the return path of input and output capacitor. d. separate the power and signal gnd. e. the switching nodes (the connection node of high/low side mosfet and inductor) is the most noisy points. keep them away from sensitive small-signal node. f. reduce parasitic r, l by minimum length, enough copper thickness and avoiding of via. 3. mosfet driver should be closed to mosfet. 4. the compensation, bypass and other function setting components should be near the ic and away from the noisy power path. figure 26. power stage ripple current path sw2 l2 sw1 l1 c out r l v out v in r in c in v
RT8801 22 ds8801-04 august 2007 www.richtek.com preliminary all brandname or trademark belong to their owner respectively figure 27. layout consideration figure 28 figure 29 figure 31 figure 30 pwm rt voss adj vdd comp fb RT8801 cspx +5v sb c bp c c r csn c out r c r fb next to ic locate next to fb pin kelvin sense l o1 v core c in locate near mosfets c boot +12v or +5v 0.1uf +12v for thermal couple vcc pwm1 gnd boot1 ugate1 phase1 lgate1 rt9607 pvcc next to ic gnd sgnd csn
RT8801 preliminary 23 ds8801-04 august 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com outline dimension e d 1 d2 e2 l b e a a1 a3 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 4.950 5.050 0.195 0.199 d2 3.400 3.750 0.134 0.148 e 4.950 5.050 0.195 0.199 e2 3.400 3.750 0.134 0.148 e 0.500 0.020 l 0.350 0.450 0.014 0.018 v-type 32l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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